ObjFW  Check-in [abd6fadbdb]

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Comment:atomic.h: Add cc to clobber list where necessary.
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SHA3-256: abd6fadbdba63e08b12915469e6ae8a22d40b0482583e6a112060aa05c1eeee1
User & Date: js on 2012-08-11 13:37:09
Other Links: manifest | tags
Context
2012-08-19
14:05
Always install autorelease.h. check-in: c7cd1e7c28 user: js tags: trunk
2012-08-11
13:37
atomic.h: Add cc to clobber list where necessary. check-in: abd6fadbdb user: js tags: trunk
11:55
runtime.h: Fix C++. check-in: c2a3a3e078 user: js tags: trunk
Changes

Modified src/atomic.h from [fe64838cdd] to [ca437e8011].

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		    "movl	%2, %%eax\n\t"
		    "orl	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "eax"
		);
# ifdef OF_AMD64_ASM
	if (sizeof(int) == 8)
		__asm__ (
		    "0:\n\t"
		    "movq	%2, %0\n\t"
		    "movq	%2, %%rax\n\t"
		    "orq	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "rax"
		);
# endif
	else
		abort();

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)







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		    "movl	%2, %%eax\n\t"
		    "orl	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "eax", "cc"
		);
# ifdef OF_AMD64_ASM
	if (sizeof(int) == 8)
		__asm__ (
		    "0:\n\t"
		    "movq	%2, %0\n\t"
		    "movq	%2, %%rax\n\t"
		    "orq	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "rax", "cc"
		);
# endif
	else
		abort();

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
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	    "movl	%2, %%eax\n\t"
	    "orl	%1, %0\n\t"
	    "lock\n\t"
	    "cmpxchg	%0, %2\n\t"
	    "jne	0\n\t"
	    : "=&r"(i)
	    : "r"(i), "m"(*p)
	    : "eax"
	);

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_or_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicOr32Barrier(i, p);







|







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	    "movl	%2, %%eax\n\t"
	    "orl	%1, %0\n\t"
	    "lock\n\t"
	    "cmpxchg	%0, %2\n\t"
	    "jne	0\n\t"
	    : "=&r"(i)
	    : "r"(i), "m"(*p)
	    : "eax", "cc"
	);

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_or_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicOr32Barrier(i, p);
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		    "movl	%2, %%eax\n\t"
		    "andl	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "eax"
		);
# ifdef OF_AMD64_ASM
	if (sizeof(int) == 8)
		__asm__ (
		    "0:\n\t"
		    "movq	%2, %0\n\t"
		    "movq	%2, %%rax\n\t"
		    "andq	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "rax"
		);
# endif
	else
		abort();

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)







|













|







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		    "movl	%2, %%eax\n\t"
		    "andl	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "eax", "cc"
		);
# ifdef OF_AMD64_ASM
	if (sizeof(int) == 8)
		__asm__ (
		    "0:\n\t"
		    "movq	%2, %0\n\t"
		    "movq	%2, %%rax\n\t"
		    "andq	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "rax", "cc"
		);
# endif
	else
		abort();

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
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	    "movl	%2, %%eax\n\t"
	    "andl	%1, %0\n\t"
	    "lock\n\t"
	    "cmpxchg	%0, %2\n\t"
	    "jne	0\n\t"
	    : "=&r"(i)
	    : "r"(i), "m"(*p)
	    : "eax"
	);

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_and_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicAnd32Barrier(i, p);







|







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	    "movl	%2, %%eax\n\t"
	    "andl	%1, %0\n\t"
	    "lock\n\t"
	    "cmpxchg	%0, %2\n\t"
	    "jne	0\n\t"
	    : "=&r"(i)
	    : "r"(i), "m"(*p)
	    : "eax", "cc"
	);

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_and_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicAnd32Barrier(i, p);
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		    "movl	%2, %%eax\n\t"
		    "xorl	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "eax"
		);
# ifdef OF_AMD64_ASM
	if (sizeof(int) == 8)
		__asm__ (
		    "0:\n\t"
		    "movq	%2, %0\n\t"
		    "movq	%2, %%rax\n\t"
		    "xorq	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "rax"
		);
# endif
	else
		abort();

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)







|













|







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		    "movl	%2, %%eax\n\t"
		    "xorl	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "eax", "cc"
		);
# ifdef OF_AMD64_ASM
	if (sizeof(int) == 8)
		__asm__ (
		    "0:\n\t"
		    "movq	%2, %0\n\t"
		    "movq	%2, %%rax\n\t"
		    "xorq	%1, %0\n\t"
		    "lock\n\t"
		    "cmpxchg	%0, %2\n\t"
		    "jne	0\n\t"
		    : "=&r"(i)
		    : "r"(i), "m"(*p)
		    : "rax", "cc"
		);
# endif
	else
		abort();

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
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	    "movl	%2, %%eax\n\t"
	    "xorl	%1, %0\n\t"
	    "lock\n\t"
	    "cmpxchgl	%0, %2\n\t"
	    "jne	0\n\t"
	    : "=&r"(i)
	    : "r"(i), "m"(*p)
	    : "eax"
	);

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_xor_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicXor32Barrier(i, p);







|







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	    "movl	%2, %%eax\n\t"
	    "xorl	%1, %0\n\t"
	    "lock\n\t"
	    "cmpxchgl	%0, %2\n\t"
	    "jne	0\n\t"
	    : "=&r"(i)
	    : "r"(i), "m"(*p)
	    : "eax", "cc"
	);

	return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_xor_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicXor32Barrier(i, p);
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	if (*p == o) {
		*p = n;
		return YES;
	}

	return NO;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
	int32_t r;

	__asm__ (
	    "xorl	%0, %0\n\t"
	    "lock\n\t"
	    "cmpxchg	%2, %3\n\t"
	    "sete	%b0\n\t"
	    "movzbl	%b0, %0"
	    : "=&d"(r)	/* use d instead of r due to gcc bug */
	    : "a"(o), "r"(n), "m"(*p)

	);

	return r;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_bool_compare_and_swap(p, o, n);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicCompareAndSwapIntBarrier(o, n, p);







|









>







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	if (*p == o) {
		*p = n;
		return YES;
	}

	return NO;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
	int r;

	__asm__ (
	    "xorl	%0, %0\n\t"
	    "lock\n\t"
	    "cmpxchg	%2, %3\n\t"
	    "sete	%b0\n\t"
	    "movzbl	%b0, %0"
	    : "=&d"(r)	/* use d instead of r due to gcc bug */
	    : "a"(o), "r"(n), "m"(*p)
	    : "cc"
	);

	return r;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_bool_compare_and_swap(p, o, n);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicCompareAndSwapIntBarrier(o, n, p);
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	    "xorl	%0, %0\n\t"
	    "lock\n\t"
	    "cmpxchg	%2, %3\n\t"
	    "sete	%b0\n\t"
	    "movzbl	%b0, %0"
	    : "=&d"(r)	/* use d instead of r due to gcc bug */
	    : "a"(o), "r"(n), "m"(*p)

	);

	return r;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_bool_compare_and_swap(p, o, n);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicCompareAndSwap32Barrier(o, n, p);







>







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	    "xorl	%0, %0\n\t"
	    "lock\n\t"
	    "cmpxchg	%2, %3\n\t"
	    "sete	%b0\n\t"
	    "movzbl	%b0, %0"
	    : "=&d"(r)	/* use d instead of r due to gcc bug */
	    : "a"(o), "r"(n), "m"(*p)
	    : "cc"
	);

	return r;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_bool_compare_and_swap(p, o, n);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicCompareAndSwap32Barrier(o, n, p);
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	    "xorl	%0, %0\n\t"
	    "lock\n\t"
	    "cmpxchg	%2, %3\n\t"
	    "sete	%b0\n\t"
	    "movzbl	%b0, %0"
	    : "=&d"(r)	/* use d instead of r due to gcc bug */
	    : "a"(o), "r"(n), "m"(*p)

	);

	return r;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_bool_compare_and_swap(p, o, n);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicCompareAndSwapPtrBarrier(o, n, p);
#else
# error No atomic operations available!
#endif
}







>











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	    "xorl	%0, %0\n\t"
	    "lock\n\t"
	    "cmpxchg	%2, %3\n\t"
	    "sete	%b0\n\t"
	    "movzbl	%b0, %0"
	    : "=&d"(r)	/* use d instead of r due to gcc bug */
	    : "a"(o), "r"(n), "m"(*p)
	    : "cc"
	);

	return r;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
	return __sync_bool_compare_and_swap(p, o, n);
#elif defined(OF_HAVE_OSATOMIC)
	return OSAtomicCompareAndSwapPtrBarrier(o, n, p);
#else
# error No atomic operations available!
#endif
}