Overview
| Comment: | OFSystemInfo: Check OS support for SSE/AVX/AVX512 |
|---|---|
| Downloads: | Tarball | ZIP archive | SQL archive |
| Timelines: | family | ancestors | descendants | both | trunk |
| Files: | files | file ages | folders |
| SHA3-256: |
42efa8c05adb97e4d2707477bbfc56c6 |
| User & Date: | js on 2023-11-10 00:25:27 |
| Other Links: | manifest | tags |
Context
|
2023-11-10
| ||
| 01:31 | OFSystemInfo: Remove check for SSE support in OS check-in: e7465cd688 user: js tags: trunk | |
| 00:25 | OFSystemInfo: Check OS support for SSE/AVX/AVX512 check-in: 42efa8c05a user: js tags: trunk | |
|
2023-11-09
| ||
| 21:09 | Use named operands for __asm__ check-in: 1b22456db6 user: js tags: trunk | |
Changes
Modified src/OFSystemInfo.h from [8467e18c65] to [e1f6b5972e].
| ︙ | ︙ | |||
234 235 236 237 238 239 240 | * @note This method is only available on AMD64 and x86. * * @return Whether the CPU supports enhanced 3DNow! */ + (bool)supportsEnhanced3DNow; /** | | < < | | < < | | < < | | < < | | < < | | < < | | < < | | < < | | 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 | * @note This method is only available on AMD64 and x86. * * @return Whether the CPU supports enhanced 3DNow! */ + (bool)supportsEnhanced3DNow; /** * @brief Returns whether the CPU and OS support SSE. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support SSE */ + (bool)supportsSSE; /** * @brief Returns whether the CPU and OS support SSE2. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support SSE2 */ + (bool)supportsSSE2; /** * @brief Returns whether the CPU and OS support SSE3. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support SSE3 */ + (bool)supportsSSE3; /** * @brief Returns whether the CPU and OS support SSSE3. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support SSSE3 */ + (bool)supportsSSSE3; /** * @brief Returns whether the CPU and OS support SSE4.1. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support SSE4.1 */ + (bool)supportsSSE41; /** * @brief Returns whether the CPU and OS support SSE4.2. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support SSE4.2 */ + (bool)supportsSSE42; /** * @brief Returns whether the CPU and OS support AVX. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX */ + (bool)supportsAVX; /** * @brief Returns whether the CPU and OS support AVX2. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX2 */ + (bool)supportsAVX2; /** * @brief Returns whether the CPU supports AES-NI. * * @note This method is only available on AMD64 and x86. |
| ︙ | ︙ | |||
342 343 344 345 346 347 348 | * @return Whether the CPU supports Intel SHA Extensions */ + (bool)supportsSHAExtensions; /** * @brief Returns whether the CPU supports fused multiply-add. * | < < | | | | > | | | | | | > | | | > | > | | > | | | | | | | | | > | | | | | | | | | | 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 | * @return Whether the CPU supports Intel SHA Extensions */ + (bool)supportsSHAExtensions; /** * @brief Returns whether the CPU supports fused multiply-add. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU supports fused multiply-add */ + (bool)supportsFusedMultiplyAdd; /** * @brief Returns whether the CPU supports F16C. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU supports F16C */ + (bool)supportsF16C; /** * @brief Returns whether the CPU and OS support AVX-512 Foundation. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Foundation */ + (bool)supportsAVX512Foundation; /** * @brief Returns whether the CPU and OS support AVX-512 Conflict Detection * Instructions. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Conflict Detection * Instructions */ + (bool)supportsAVX512ConflictDetectionInstructions; /** * @brief Returns whether the CPU and OS support AVX-512 Exponential and * Reciprocal Instructions. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Exponential and Reciprocal * Instructions */ + (bool)supportsAVX512ExponentialAndReciprocalInstructions; /** * @brief Returns whether the CPU and OS support AVX-512 Prefetch Instructions. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Prefetch Instructions */ + (bool)supportsAVX512PrefetchInstructions; /** * @brief Returns whether the CPU and OS support AVX-512 Vector Length * Extensions. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Vector Length Extensions */ + (bool)supportsAVX512VectorLengthExtensions; /** * @brief Returns whether the CPU and OS support AVX-512 Doubleword and Quadword * Instructions. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Doubleword and Quadword * Instructions */ + (bool)supportsAVX512DoublewordAndQuadwordInstructions; /** * @brief Returns whether the CPU and OS support AVX-512 Byte and Word * Instructions. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Byte and Word Instructions */ + (bool)supportsAVX512ByteAndWordInstructions; /** * @brief Returns whether the CPU and OS support AVX-512 Integer Fused * Multiply-Add. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Integer Fused Multiply-Add */ + (bool)supportsAVX512IntegerFusedMultiplyAdd; /** * @brief Returns whether the CPU and OS support AVX-512 Vector Byte * Manipulation Instructions. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Vector Byte Manipulation * Instructions */ + (bool)supportsAVX512VectorByteManipulationInstructions; /** * @brief Returns whether the CPU and OS support the AVX-512 Vector Population * Count Instruction. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 the Vector Population Count * Instruction */ + (bool)supportsAVX512VectorPopulationCountInstruction; /** * @brief Returns whether the CPU and OS support AVX-512 Vector Neural Network * Instructions. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Vector Neural Network * Instructions */ + (bool)supportsAVX512VectorNeuralNetworkInstructions; /** * @brief Returns whether the CPU and OS support AVX-512 Vector Byte * Manipulation Instructions 2. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Vector Byte Manipulation * Instructions 2 */ + (bool)supportsAVX512VectorByteManipulationInstructions2; /** * @brief Returns whether the CPU and OS support AVX-512 Bit Algorithms. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Bit Algorithms */ + (bool)supportsAVX512BitAlgorithms; /** * @brief Returns whether the CPU and OS support AVX-512 Float16 Instructions. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 Float16 Instructions */ + (bool)supportsAVX512Float16Instructions; /** * @brief Returns whether the CPU and OS support AVX-512 BFloat16 Instructions. * * @note This method is only available on AMD64 and x86. * * @return Whether the CPU and OS support AVX-512 BFloat16 Instructions */ + (bool)supportsAVX512BFloat16Instructions; #endif #if defined(OF_POWERPC) || defined(OF_POWERPC64) || defined(DOXYGEN) /** * @brief Returns whether the CPU and OS support AltiVec. |
| ︙ | ︙ |
Modified src/OFSystemInfo.m from [4a5cc32620] to [dde9f4593e].
| ︙ | ︙ | |||
314 315 316 317 318 319 320 321 322 323 324 325 326 327 |
);
# else
memset(®s, 0, sizeof(regs));
# endif
return regs;
}
#endif
@implementation OFSystemInfo
+ (void)initialize
{
long tmp;
| > > > > > > > > > > > > > > > > > > | 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 |
);
# else
memset(®s, 0, sizeof(regs));
# endif
return regs;
}
static OF_INLINE struct X86Regs
x86XCR(uint32_t ecx)
{
struct X86Regs regs = { 0 };
if (!(x86CPUID(1, 0).ecx & (1u << 27)))
return regs;
__asm__ (
"xgetbv"
: "=a" (regs.eax),
"=d" (regs.edx)
: "c" (ecx)
);
return regs;
}
#endif
@implementation OFSystemInfo
+ (void)initialize
{
long tmp;
|
| ︙ | ︙ | |||
755 756 757 758 759 760 761 |
{
return (x86CPUID(0x80000000, 0).eax >= 0x80000001 &&
x86CPUID(0x80000001, 0).edx & (1u << 30));
}
+ (bool)supportsSSE
{
| | > | > | > | > | > | > | > | > | 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 |
{
return (x86CPUID(0x80000000, 0).eax >= 0x80000001 &&
x86CPUID(0x80000001, 0).edx & (1u << 30));
}
+ (bool)supportsSSE
{
return ((x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).edx & (1u << 25)) &&
x86XCR(0).eax & (1u << 1));
}
+ (bool)supportsSSE2
{
return ((x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).edx & (1u << 26)) &&
x86XCR(0).eax & (1u << 1));
}
+ (bool)supportsSSE3
{
return ((x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 0)) &&
x86XCR(0).eax & (1u << 1));
}
+ (bool)supportsSSSE3
{
return ((x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 9)) &&
x86XCR(0).eax & (1u << 1));
}
+ (bool)supportsSSE41
{
return ((x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 19)) &&
x86XCR(0).eax & (1u << 1));
}
+ (bool)supportsSSE42
{
return ((x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 20)) &&
x86XCR(0).eax & (1u << 1));
}
+ (bool)supportsAVX
{
return ((x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 28)) &&
x86XCR(0).eax & (1u << 2));
}
+ (bool)supportsAVX2
{
return ((x86CPUID(0, 0).eax >= 7 && (x86CPUID(7, 0).ebx & (1u << 5))) &&
x86XCR(0).eax & (1u << 2));
}
+ (bool)supportsAESNI
{
return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 25));
}
|
| ︙ | ︙ | |||
815 816 817 818 819 820 821 |
+ (bool)supportsF16C
{
return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 29));
}
+ (bool)supportsAVX512Foundation
{
| | > | > | > | > | > | > | > | > | > | > | > | > | > | > | > | 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 |
+ (bool)supportsF16C
{
return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 29));
}
+ (bool)supportsAVX512Foundation
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 16)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512ConflictDetectionInstructions
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 28)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512ExponentialAndReciprocalInstructions
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 27)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512PrefetchInstructions
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 26)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512VectorLengthExtensions
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 31)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512DoublewordAndQuadwordInstructions
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 17)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512ByteAndWordInstructions
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 30)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512IntegerFusedMultiplyAdd
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 21)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512VectorByteManipulationInstructions
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ecx & (1u << 1)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512VectorPopulationCountInstruction
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ecx & (1u << 14)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512VectorNeuralNetworkInstructions
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ecx & (1u << 11)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512VectorByteManipulationInstructions2
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ecx & (1u << 6)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512BitAlgorithms
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ecx & (1u << 12)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512Float16Instructions
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).edx & (1u << 23)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
+ (bool)supportsAVX512BFloat16Instructions
{
return ((x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 1).eax & (1u << 5)) &&
x86XCR(0).eax & ((1u << 5) | (1u << 6) | (1u << 7)));
}
#endif
#if defined(OF_POWERPC) || defined(OF_POWERPC64)
+ (bool)supportsAltiVec
{
# if defined(OF_MACOS)
|
| ︙ | ︙ |