Index: src/OFSystemInfo.h ================================================================== --- src/OFSystemInfo.h +++ src/OFSystemInfo.h @@ -54,10 +54,33 @@ @property (class, readonly, nonatomic) bool supportsSSE42; @property (class, readonly, nonatomic) bool supportsAVX; @property (class, readonly, nonatomic) bool supportsAVX2; @property (class, readonly, nonatomic) bool supportsAESNI; @property (class, readonly, nonatomic) bool supportsSHAExtensions; +@property (class, readonly, nonatomic) bool supportsAVX512Foundation; +@property (class, readonly, nonatomic) + bool supportsAVX512ConflictDetectionInstructions; +@property (class, readonly, nonatomic) + bool supportsAVX512ExponentialAndReciprocalInstructions; +@property (class, readonly, nonatomic) bool supportsAVX512PrefetchInstructions; +@property (class, readonly, nonatomic) + bool supportsAVX512VectorLengthExtensions; +@property (class, readonly, nonatomic) + bool supportsAVX512DoublewordAndQuadwordInstructions; +@property (class, readonly, nonatomic) + bool supportsAVX512ByteAndWordInstructions; +@property (class, readonly, nonatomic) + bool supportsAVX512IntegerFusedMultiplyAdd; +@property (class, readonly, nonatomic) + bool supportsAVX512VectorByteManipulationInstructions; +@property (class, readonly, nonatomic) + bool supportsAVX512VectorPopulationCountInstruction; +@property (class, readonly, nonatomic) + bool supportsAVX512VectorNeuralNetworkInstructions; +@property (class, readonly, nonatomic) + bool supportsAVX512VectorByteManipulationInstructions2; +@property (class, readonly, nonatomic) bool supportsAVX512BitAlgorithms; # endif # if defined(OF_POWERPC) || defined(OF_POWERPC64) || defined(DOXYGEN) @property (class, readonly, nonatomic) bool supportsAltiVec; # endif # if defined(OF_WINDOWS) || defined(DOXYGEN) @@ -313,10 +336,138 @@ * @note This method is only available on AMD64 and x86. * * @return Whether the CPU supports Intel SHA Extensions */ + (bool)supportsSHAExtensions; + +/** + * @brief Returns whether the CPU supports AVX-512 Foundation. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Foundation + */ ++ (bool)supportsAVX512Foundation; + +/** + * @brief Returns whether the CPU supports AVX-512 Conflict Detection + * Instructions. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Conflict Detection Instructions + */ ++ (bool)supportsAVX512ConflictDetectionInstructions; + +/** + * @brief Returns whether the CPU supports AVX-512 Exponential and Reciprocal + * Instructions. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Exponential and Reciprocal + * Instructions + */ ++ (bool)supportsAVX512ExponentialAndReciprocalInstructions; + +/** + * @brief Returns whether the CPU supports AVX-512 Prefetch Instructions. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Prefetch Instructions + */ ++ (bool)supportsAVX512PrefetchInstructions; + +/** + * @brief Returns whether the CPU supports AVX-512 Vector Length Extensions. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Vector Length Extensions + */ ++ (bool)supportsAVX512VectorLengthExtensions; + +/** + * @brief Returns whether the CPU supports AVX-512 Doubleword and Quadword + * Instructions. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Doubleword and Quadword Instructions + */ ++ (bool)supportsAVX512DoublewordAndQuadwordInstructions; + +/** + * @brief Returns whether the CPU supports AVX-512 Byte and Word Instructions. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Byte and Word Instructions + */ ++ (bool)supportsAVX512ByteAndWordInstructions; + +/** + * @brief Returns whether the CPU supports AVX-512 Integer Fused Multiply Add. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Integer Fused Multiply Add + */ ++ (bool)supportsAVX512IntegerFusedMultiplyAdd; + +/** + * @brief Returns whether the CPU supports AVX-512 Vector Byte Manipulation + * Instructions. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Vector Byte Manipulation + * Instructions + */ ++ (bool)supportsAVX512VectorByteManipulationInstructions; + +/** + * @brief Returns whether the CPU supports the AVX-512 Vector Population Count + * Instruction. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 the Vector Population Count + * Instruction + */ ++ (bool)supportsAVX512VectorPopulationCountInstruction; + +/** + * @brief Returns whether the CPU supports AVX-512 Vector Neural Network + * Instructions. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Vector Neural Network Instructions + */ ++ (bool)supportsAVX512VectorNeuralNetworkInstructions; + +/** + * @brief Returns whether the CPU supports AVX-512 Vector Byte Manipulation + * Instructions 2. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Vector Byte Manipulation + * Instructions 2 + */ ++ (bool)supportsAVX512VectorByteManipulationInstructions2; + +/** + * @brief Returns whether the CPU supports AVX-512 Bit Algorithms. + * + * @note This method is only available on AMD64 and x86. + * + * @return Whether the CPU supports AVX-512 Bit Algorithms + */ ++ (bool)supportsAVX512BitAlgorithms; #endif #if defined(OF_POWERPC) || defined(OF_POWERPC64) || defined(DOXYGEN) /** * @brief Returns whether the CPU and OS support AltiVec. Index: src/OFSystemInfo.m ================================================================== --- src/OFSystemInfo.m +++ src/OFSystemInfo.m @@ -732,11 +732,11 @@ } #if defined(OF_AMD64) || defined(OF_X86) + (bool)supportsMMX { - return (x86CPUID(1, 0).edx & (1u << 23)); + return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).edx & (1u << 23)); } + (bool)supports3DNow { return (x86CPUID(0x80000001, 0).edx & (1u << 31)); @@ -747,56 +747,121 @@ return (x86CPUID(0x80000001, 0).edx & (1u << 30)); } + (bool)supportsSSE { - return (x86CPUID(1, 0).edx & (1u << 25)); + return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).edx & (1u << 25)); } + (bool)supportsSSE2 { - return (x86CPUID(1, 0).edx & (1u << 26)); + return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).edx & (1u << 26)); } + (bool)supportsSSE3 { - return (x86CPUID(1, 0).ecx & (1u << 0)); + return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 0)); } + (bool)supportsSSSE3 { - return (x86CPUID(1, 0).ecx & (1u << 9)); + return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 9)); } + (bool)supportsSSE41 { - return (x86CPUID(1, 0).ecx & (1u << 19)); + return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 19)); } + (bool)supportsSSE42 { - return (x86CPUID(1, 0).ecx & (1u << 20)); + return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 20)); } + (bool)supportsAVX { - return (x86CPUID(1, 0).ecx & (1u << 28)); + return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 28)); } + (bool)supportsAVX2 { - return x86CPUID(0, 0).eax >= 7 && (x86CPUID(7, 0).ebx & (1u << 5)); + return (x86CPUID(0, 0).eax >= 7 && (x86CPUID(7, 0).ebx & (1u << 5))); } + (bool)supportsAESNI { - return (x86CPUID(1, 0).ecx & (1u << 25)); + return (x86CPUID(0, 0).eax >= 1 && x86CPUID(1, 0).ecx & (1u << 25)); } + (bool)supportsSHAExtensions { - return (x86CPUID(7, 0).ebx & (1u << 29)); + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 29)); +} + ++ (bool)supportsAVX512Foundation +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 16)); +} + ++ (bool)supportsAVX512ConflictDetectionInstructions +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 28)); +} + ++ (bool)supportsAVX512ExponentialAndReciprocalInstructions +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 27)); +} + ++ (bool)supportsAVX512PrefetchInstructions +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 26)); +} + ++ (bool)supportsAVX512VectorLengthExtensions +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 31)); +} + ++ (bool)supportsAVX512DoublewordAndQuadwordInstructions +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 17)); +} + ++ (bool)supportsAVX512ByteAndWordInstructions +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 30)); +} + ++ (bool)supportsAVX512IntegerFusedMultiplyAdd +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ebx & (1u << 21)); +} + ++ (bool)supportsAVX512VectorByteManipulationInstructions +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ecx & (1u << 1)); +} + ++ (bool)supportsAVX512VectorPopulationCountInstruction +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ecx & (1u << 14)); +} + ++ (bool)supportsAVX512VectorNeuralNetworkInstructions +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ecx & (1u << 11)); +} + ++ (bool)supportsAVX512VectorByteManipulationInstructions2 +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ecx & (1u << 6)); +} + ++ (bool)supportsAVX512BitAlgorithms +{ + return (x86CPUID(0, 0).eax >= 7 && x86CPUID(7, 0).ecx & (1u << 12)); } #endif #if defined(OF_POWERPC) || defined(OF_POWERPC64) + (bool)supportsAltiVec Index: tests/OFSystemInfoTests.m ================================================================== --- tests/OFSystemInfoTests.m +++ tests/OFSystemInfoTests.m @@ -121,10 +121,69 @@ [OFStdOut writeFormat: @"[OFSystemInfo] Supports AES-NI: %d\n", [OFSystemInfo supportsAESNI]]; [OFStdOut writeFormat: @"[OFSystemInfo] Supports SHA extensions: %d\n", [OFSystemInfo supportsSHAExtensions]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Foundation: %d\n", + [OFSystemInfo supportsAVX512Foundation]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Conflict Detection Instructions: " + @"%d\n", + [OFSystemInfo supportsAVX512ConflictDetectionInstructions]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Exponential and Reciprocal " + @"Instructions: %d\n", + [OFSystemInfo supportsAVX512ExponentialAndReciprocalInstructions]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Prefetch Instructions: %d\n", + [OFSystemInfo supportsAVX512PrefetchInstructions]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Vector Length Extensions: %d\n", + [OFSystemInfo supportsAVX512VectorLengthExtensions]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Doubleword and Quadword " + @"Instructions: %d\n", + [OFSystemInfo supportsAVX512DoublewordAndQuadwordInstructions]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Byte and Word Instructions: %d\n", + [OFSystemInfo supportsAVX512ByteAndWordInstructions]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Integer Fused Multiply Add: %d\n", + [OFSystemInfo supportsAVX512IntegerFusedMultiplyAdd]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Vector Byte Manipulation " + @"Instructions: %d\n", + [OFSystemInfo supportsAVX512VectorByteManipulationInstructions]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Vector Population Count " + @"Instruction: %d\n", + [OFSystemInfo supportsAVX512VectorPopulationCountInstruction]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Vector Neutral Network " + @"Instructions: %d\n", + [OFSystemInfo supportsAVX512VectorNeuralNetworkInstructions]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Vector Byte Manipulation " + @"Instructions 2: %d\n", + [OFSystemInfo supportsAVX512VectorByteManipulationInstructions2]]; + + [OFStdOut writeFormat: + @"[OFSystemInfo] Supports AVX-512 Bit Algorithms: %d\n", + [OFSystemInfo supportsAVX512BitAlgorithms]]; #endif #ifdef OF_POWERPC [OFStdOut writeFormat: @"[OFSystemInfo] Supports AltiVec: %d\n", [OFSystemInfo supportsAltiVec]];