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|
#endif
static OF_INLINE int
of_atomic_add_int(volatile int *p, int i)
{
#if !defined(OF_HAVE_THREADS)
return (*p += i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
if (sizeof(int) == 4)
__asm__ __volatile__ (
"lock\n\t"
"xaddl %0, %2\n\t"
"addl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
# ifdef OF_AMD64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"lock\n\t"
"xaddq %0, %2\n\t"
"addq %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
|
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|
#endif
static OF_INLINE int
of_atomic_add_int(volatile int *p, int i)
{
#if !defined(OF_HAVE_THREADS)
return (*p += i);
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
if (sizeof(int) == 4)
__asm__ __volatile__ (
"lock\n\t"
"xaddl %0, %2\n\t"
"addl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
# ifdef OF_X86_64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"lock\n\t"
"xaddq %0, %2\n\t"
"addq %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
|
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|
}
static OF_INLINE int32_t
of_atomic_add_32(volatile int32_t *p, int32_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*p += i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ __volatile__ (
"lock\n\t"
"xaddl %0, %2\n\t"
"addl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
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|
}
static OF_INLINE int32_t
of_atomic_add_32(volatile int32_t *p, int32_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*p += i);
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
__asm__ __volatile__ (
"lock\n\t"
"xaddl %0, %2\n\t"
"addl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
|
| ︙ | | | ︙ | |
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|
}
static OF_INLINE void*
of_atomic_add_ptr(void* volatile *p, intptr_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*(char* volatile*)p += i);
#elif defined(OF_X86_ASM)
__asm__ __volatile__ (
"lock\n\t"
"xaddl %0, %2\n\t"
"addl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
return (void*)i;
#elif defined(OF_AMD64_ASM)
__asm__ __volatile__ (
"lock\n\t"
"xaddq %0, %2\n\t"
"addq %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
return (void*)i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_add_and_fetch(p, (void*)i);
|
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|
}
static OF_INLINE void*
of_atomic_add_ptr(void* volatile *p, intptr_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*(char* volatile*)p += i);
#elif defined(OF_X86_64_ASM)
__asm__ __volatile__ (
"lock\n\t"
"xaddq %0, %2\n\t"
"addq %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
return (void*)i;
#elif defined(OF_X86_ASM)
__asm__ __volatile__ (
"lock\n\t"
"xaddl %0, %2\n\t"
"addl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
return (void*)i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_add_and_fetch(p, (void*)i);
|
| ︙ | | | ︙ | |
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|
}
static OF_INLINE int
of_atomic_sub_int(volatile int *p, int i)
{
#if !defined(OF_HAVE_THREADS)
return (*p -= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
if (sizeof(int) == 4)
__asm__ __volatile__ (
"negl %0\n\t"
"lock\n\t"
"xaddl %0, %2\n\t"
"subl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
# ifdef OF_AMD64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"negq %0\n\t"
"lock\n\t"
"xaddq %0, %2\n\t"
"subq %1, %0"
: "+&r"(i)
|
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|
|
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|
}
static OF_INLINE int
of_atomic_sub_int(volatile int *p, int i)
{
#if !defined(OF_HAVE_THREADS)
return (*p -= i);
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
if (sizeof(int) == 4)
__asm__ __volatile__ (
"negl %0\n\t"
"lock\n\t"
"xaddl %0, %2\n\t"
"subl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
# ifdef OF_X86_64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"negq %0\n\t"
"lock\n\t"
"xaddq %0, %2\n\t"
"subq %1, %0"
: "+&r"(i)
|
| ︙ | | | ︙ | |
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|
}
static OF_INLINE int32_t
of_atomic_sub_32(volatile int32_t *p, int32_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*p -= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ __volatile__ (
"negl %0\n\t"
"lock\n\t"
"xaddl %0, %2\n\t"
"subl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
|
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|
}
static OF_INLINE int32_t
of_atomic_sub_32(volatile int32_t *p, int32_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*p -= i);
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
__asm__ __volatile__ (
"negl %0\n\t"
"lock\n\t"
"xaddl %0, %2\n\t"
"subl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
|
| ︙ | | | ︙ | |
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|
}
static OF_INLINE void*
of_atomic_sub_ptr(void* volatile *p, intptr_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*(char* volatile*)p -= i);
#elif defined(OF_X86_ASM)
__asm__ __volatile__ (
"negl %0\n\t"
"lock\n\t"
"xaddl %0, %2\n\t"
"subl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
return (void*)i;
#elif defined(OF_AMD64_ASM)
__asm__ __volatile__ (
"negq %0\n\t"
"lock\n\t"
"xaddq %0, %2\n\t"
"subq %1, %0"
: "+&r"(i)
|
>
>
>
>
>
>
>
>
>
>
>
<
<
<
<
<
<
<
<
<
<
<
|
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|
}
static OF_INLINE void*
of_atomic_sub_ptr(void* volatile *p, intptr_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*(char* volatile*)p -= i);
#elif defined(OF_X86_64_ASM)
__asm__ __volatile__ (
"negq %0\n\t"
"lock\n\t"
"xaddq %0, %2\n\t"
"subq %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
return (void*)i;
#elif defined(OF_X86_ASM)
__asm__ __volatile__ (
"negl %0\n\t"
"lock\n\t"
"xaddl %0, %2\n\t"
"subl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
return (void*)i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_sub_and_fetch(p, (void*)i);
#elif defined(OF_HAVE_OSATOMIC)
|
| ︙ | | | ︙ | |
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|
}
static OF_INLINE int
of_atomic_inc_int(volatile int *p)
{
#if !defined(OF_HAVE_THREADS)
return ++*p;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
int i;
if (sizeof(int) == 4)
__asm__ __volatile__ (
"xorl %0, %0\n\t"
"incl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
"incl %0"
: "=&r"(i)
: "m"(*p)
);
# ifdef OF_AMD64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"xorq %0, %0\n\t"
"incq %0\n\t"
"lock\n\t"
"xaddq %0, %1\n\t"
"incq %0"
|
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|
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|
}
static OF_INLINE int
of_atomic_inc_int(volatile int *p)
{
#if !defined(OF_HAVE_THREADS)
return ++*p;
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
int i;
if (sizeof(int) == 4)
__asm__ __volatile__ (
"xorl %0, %0\n\t"
"incl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
"incl %0"
: "=&r"(i)
: "m"(*p)
);
# ifdef OF_X86_64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"xorq %0, %0\n\t"
"incq %0\n\t"
"lock\n\t"
"xaddq %0, %1\n\t"
"incq %0"
|
| ︙ | | | ︙ | |
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|
}
static OF_INLINE int32_t
of_atomic_inc_32(volatile int32_t *p)
{
#if !defined(OF_HAVE_THREADS)
return ++*p;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
uint32_t i;
__asm__ __volatile__ (
"xorl %0, %0\n\t"
"incl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
|
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|
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|
}
static OF_INLINE int32_t
of_atomic_inc_32(volatile int32_t *p)
{
#if !defined(OF_HAVE_THREADS)
return ++*p;
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
uint32_t i;
__asm__ __volatile__ (
"xorl %0, %0\n\t"
"incl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
|
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|
}
static OF_INLINE int
of_atomic_dec_int(volatile int *p)
{
#if !defined(OF_HAVE_THREADS)
return --*p;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
int i;
if (sizeof(int) == 4)
__asm__ __volatile__ (
"xorl %0, %0\n\t"
"decl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
"decl %0"
: "=&r"(i)
: "m"(*p)
);
# ifdef OF_AMD64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"xorq %0, %0\n\t"
"decq %0\n\t"
"lock\n\t"
"xaddq %0, %1\n\t"
"decq %0"
|
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|
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|
}
static OF_INLINE int
of_atomic_dec_int(volatile int *p)
{
#if !defined(OF_HAVE_THREADS)
return --*p;
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
int i;
if (sizeof(int) == 4)
__asm__ __volatile__ (
"xorl %0, %0\n\t"
"decl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
"decl %0"
: "=&r"(i)
: "m"(*p)
);
# ifdef OF_X86_64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"xorq %0, %0\n\t"
"decq %0\n\t"
"lock\n\t"
"xaddq %0, %1\n\t"
"decq %0"
|
| ︙ | | | ︙ | |
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|
}
static OF_INLINE int32_t
of_atomic_dec_32(volatile int32_t *p)
{
#if !defined(OF_HAVE_THREADS)
return --*p;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
uint32_t i;
__asm__ __volatile__ (
"xorl %0, %0\n\t"
"decl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
|
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|
}
static OF_INLINE int32_t
of_atomic_dec_32(volatile int32_t *p)
{
#if !defined(OF_HAVE_THREADS)
return --*p;
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
uint32_t i;
__asm__ __volatile__ (
"xorl %0, %0\n\t"
"decl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
|
| ︙ | | | ︙ | |
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|
}
static OF_INLINE unsigned int
of_atomic_or_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_HAVE_THREADS)
return (*p |= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
if (sizeof(int) == 4)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"orl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax", "cc"
);
# ifdef OF_AMD64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"0:\n\t"
"movq %2, %0\n\t"
"movq %0, %%rax\n\t"
"orq %1, %0\n\t"
"lock\n\t"
|
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|
|
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400
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|
}
static OF_INLINE unsigned int
of_atomic_or_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_HAVE_THREADS)
return (*p |= i);
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
if (sizeof(int) == 4)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"orl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax", "cc"
);
# ifdef OF_X86_64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"0:\n\t"
"movq %2, %0\n\t"
"movq %0, %%rax\n\t"
"orq %1, %0\n\t"
"lock\n\t"
|
| ︙ | | | ︙ | |
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435
|
}
static OF_INLINE uint32_t
of_atomic_or_32(volatile uint32_t *p, uint32_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*p |= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"orl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
|
|
|
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|
}
static OF_INLINE uint32_t
of_atomic_or_32(volatile uint32_t *p, uint32_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*p |= i);
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"orl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
|
| ︙ | | | ︙ | |
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|
}
static OF_INLINE unsigned int
of_atomic_and_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_HAVE_THREADS)
return (*p &= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
if (sizeof(int) == 4)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"andl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax", "cc"
);
# ifdef OF_AMD64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"0:\n\t"
"movq %2, %0\n\t"
"movq %0, %%rax\n\t"
"andq %1, %0\n\t"
"lock\n\t"
|
|
|
|
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|
}
static OF_INLINE unsigned int
of_atomic_and_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_HAVE_THREADS)
return (*p &= i);
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
if (sizeof(int) == 4)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"andl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax", "cc"
);
# ifdef OF_X86_64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"0:\n\t"
"movq %2, %0\n\t"
"movq %0, %%rax\n\t"
"andq %1, %0\n\t"
"lock\n\t"
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}
static OF_INLINE uint32_t
of_atomic_and_32(volatile uint32_t *p, uint32_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*p &= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"andl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
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}
static OF_INLINE uint32_t
of_atomic_and_32(volatile uint32_t *p, uint32_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*p &= i);
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"andl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
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}
static OF_INLINE unsigned int
of_atomic_xor_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_HAVE_THREADS)
return (*p ^= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
if (sizeof(int) == 4)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"xorl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax", "cc"
);
# ifdef OF_AMD64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"0:\n\t"
"movq %2, %0\n\t"
"movq %0, %%rax\n\t"
"xorq %1, %0\n\t"
"lock\n\t"
|
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|
}
static OF_INLINE unsigned int
of_atomic_xor_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_HAVE_THREADS)
return (*p ^= i);
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
if (sizeof(int) == 4)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"xorl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax", "cc"
);
# ifdef OF_X86_64_ASM
else if (sizeof(int) == 8)
__asm__ __volatile__ (
"0:\n\t"
"movq %2, %0\n\t"
"movq %0, %%rax\n\t"
"xorq %1, %0\n\t"
"lock\n\t"
|
| ︙ | | | ︙ | |
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}
static OF_INLINE uint32_t
of_atomic_xor_32(volatile uint32_t *p, uint32_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*p ^= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"xorl %1, %0\n\t"
"lock\n\t"
"cmpxchgl %0, %2\n\t"
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}
static OF_INLINE uint32_t
of_atomic_xor_32(volatile uint32_t *p, uint32_t i)
{
#if !defined(OF_HAVE_THREADS)
return (*p ^= i);
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
__asm__ __volatile__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %0, %%eax\n\t"
"xorl %1, %0\n\t"
"lock\n\t"
"cmpxchgl %0, %2\n\t"
|
| ︙ | | | ︙ | |
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#if !defined(OF_HAVE_THREADS)
if (*p == o) {
*p = n;
return true;
}
return false;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
int r;
__asm__ __volatile__ (
"lock\n\t"
"cmpxchg %2, %3\n\t"
"sete %b0\n\t"
"movzbl %b0, %0"
|
|
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#if !defined(OF_HAVE_THREADS)
if (*p == o) {
*p = n;
return true;
}
return false;
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
int r;
__asm__ __volatile__ (
"lock\n\t"
"cmpxchg %2, %3\n\t"
"sete %b0\n\t"
"movzbl %b0, %0"
|
| ︙ | | | ︙ | |
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#if !defined(OF_HAVE_THREADS)
if (*p == o) {
*p = n;
return true;
}
return false;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
int r;
__asm__ __volatile__ (
"lock\n\t"
"cmpxchg %2, %3\n\t"
"sete %b0\n\t"
"movzbl %b0, %0"
|
|
|
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#if !defined(OF_HAVE_THREADS)
if (*p == o) {
*p = n;
return true;
}
return false;
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
int r;
__asm__ __volatile__ (
"lock\n\t"
"cmpxchg %2, %3\n\t"
"sete %b0\n\t"
"movzbl %b0, %0"
|
| ︙ | | | ︙ | |
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|
#if !defined(OF_HAVE_THREADS)
if (*p == o) {
*p = n;
return true;
}
return false;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
int r;
__asm__ __volatile__ (
"lock\n\t"
"cmpxchg %2, %3\n\t"
"sete %b0\n\t"
"movzbl %b0, %0"
|
|
|
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|
#if !defined(OF_HAVE_THREADS)
if (*p == o) {
*p = n;
return true;
}
return false;
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
int r;
__asm__ __volatile__ (
"lock\n\t"
"cmpxchg %2, %3\n\t"
"sete %b0\n\t"
"movzbl %b0, %0"
|
| ︙ | | | ︙ | |
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#endif
}
static OF_INLINE void
of_memory_barrier(void)
{
#if !defined(OF_HAVE_THREADS)
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ __volatile__ (
"mfence"
);
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
__sync_synchronize();
#elif defined(OF_HAVE_OSATOMIC)
OSMemoryBarrier();
#else
# error of_memory_barrier not implemented!
#endif
}
static OF_INLINE void
of_memory_read_barrier(void)
{
#if !defined(OF_HAVE_THREADS)
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ __volatile__ (
"lfence"
);
#else
of_memory_barrier();
#endif
}
static OF_INLINE void
of_memory_write_barrier(void)
{
#if !defined(OF_HAVE_THREADS)
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ __volatile__ (
"sfence"
);
#else
of_memory_barrier();
#endif
}
|
|
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|
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#endif
}
static OF_INLINE void
of_memory_barrier(void)
{
#if !defined(OF_HAVE_THREADS)
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
__asm__ __volatile__ (
"mfence"
);
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
__sync_synchronize();
#elif defined(OF_HAVE_OSATOMIC)
OSMemoryBarrier();
#else
# error of_memory_barrier not implemented!
#endif
}
static OF_INLINE void
of_memory_read_barrier(void)
{
#if !defined(OF_HAVE_THREADS)
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
__asm__ __volatile__ (
"lfence"
);
#else
of_memory_barrier();
#endif
}
static OF_INLINE void
of_memory_write_barrier(void)
{
#if !defined(OF_HAVE_THREADS)
#elif defined(OF_X86_64_ASM) || defined(OF_X86_ASM)
__asm__ __volatile__ (
"sfence"
);
#else
of_memory_barrier();
#endif
}
|