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static OF_INLINE int
of_atomic_add_int(volatile int *p, int i)
{
#if !defined(OF_THREADS)
return (*p += i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ (
"lock\n\t"
"xaddl %0, %2\n\t"
"addl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_add_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicAdd32Barrier(i, p);
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static OF_INLINE int
of_atomic_add_int(volatile int *p, int i)
{
#if !defined(OF_THREADS)
return (*p += i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
if (sizeof(int) == 4)
__asm__ (
"lock\n\t"
"xaddl %0, %2\n\t"
"addl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
# ifdef OF_AMD64_ASM
else if (sizeof(int) == 8)
__asm__ (
"lock\n\t"
"xaddq %0, %2\n\t"
"addq %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
# endif
else
abort();
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_add_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicAdd32Barrier(i, p);
|
| ︙ | | | ︙ | |
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static OF_INLINE int
of_atomic_sub_int(volatile int *p, int i)
{
#if !defined(OF_THREADS)
return (*p -= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ (
"negl %0\n\t"
"lock\n\t"
"xaddl %0, %2\n\t"
"subl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_sub_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicAdd32Barrier(-i, p);
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static OF_INLINE int
of_atomic_sub_int(volatile int *p, int i)
{
#if !defined(OF_THREADS)
return (*p -= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
if (sizeof(int) == 4)
__asm__ (
"negl %0\n\t"
"lock\n\t"
"xaddl %0, %2\n\t"
"subl %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
# ifdef OF_AMD64_ASM
else if (sizeof(int) == 8)
__asm__ (
"negq %0\n\t"
"lock\n\t"
"xaddq %0, %2\n\t"
"subq %1, %0"
: "+&r"(i)
: "r"(i), "m"(*p)
);
# endif
else
abort();
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_sub_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicAdd32Barrier(-i, p);
|
| ︙ | | | ︙ | |
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223
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|
of_atomic_inc_int(volatile int *p)
{
#if !defined(OF_THREADS)
return ++*p;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
uint32_t i;
__asm__ (
"xorl %0, %0\n\t"
"incl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
"incl %0"
: "=&r"(i)
: "m"(*p)
);
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_add_and_fetch(p, 1);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicIncrement32Barrier(p);
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|
of_atomic_inc_int(volatile int *p)
{
#if !defined(OF_THREADS)
return ++*p;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
uint32_t i;
if (sizeof(int) == 4)
__asm__ (
"xorl %0, %0\n\t"
"incl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
"incl %0"
: "=&r"(i)
: "m"(*p)
);
# ifdef OF_AMD64_ASM
else if (sizeof(int) == 8)
__asm__ (
"xorq %0, %0\n\t"
"incq %0\n\t"
"lock\n\t"
"xaddq %0, %1\n\t"
"incq %0"
: "=&r"(i)
: "m"(*p)
);
# endif
else
abort();
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_add_and_fetch(p, 1);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicIncrement32Barrier(p);
|
| ︙ | | | ︙ | |
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275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
|
of_atomic_dec_int(volatile int *p)
{
#if !defined(OF_THREADS)
return --*p;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
uint32_t i;
__asm__ (
"xorl %0, %0\n\t"
"decl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
"decl %0"
: "=&r"(i)
: "m"(*p)
);
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_sub_and_fetch(p, 1);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicDecrement32Barrier(p);
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|
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|
of_atomic_dec_int(volatile int *p)
{
#if !defined(OF_THREADS)
return --*p;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
uint32_t i;
if (sizeof(int) == 4)
__asm__ (
"xorl %0, %0\n\t"
"decl %0\n\t"
"lock\n\t"
"xaddl %0, %1\n\t"
"decl %0"
: "=&r"(i)
: "m"(*p)
);
# ifdef OF_AMD64_ASM
else if (sizeof(int) == 8)
__asm__ (
"xorq %0, %0\n\t"
"decq %0\n\t"
"lock\n\t"
"xaddq %0, %1\n\t"
"decq %0"
: "=&r"(i)
: "m"(*p)
);
# endif
else
abort();
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_sub_and_fetch(p, 1);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicDecrement32Barrier(p);
|
| ︙ | | | ︙ | |
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343
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353
354
355
|
static OF_INLINE unsigned int
of_atomic_or_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_THREADS)
return (*p |= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %2, %%eax\n\t"
"orl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax"
);
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_or_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicOr32Barrier(i, p);
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>
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|
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427
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|
static OF_INLINE unsigned int
of_atomic_or_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_THREADS)
return (*p |= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
if (sizeof(int) == 4)
__asm__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %2, %%eax\n\t"
"orl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax"
);
# ifdef OF_AMD64_ASM
if (sizeof(int) == 8)
__asm__ (
"0:\n\t"
"movq %2, %0\n\t"
"movq %2, %%rax\n\t"
"orq %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "rax"
);
# endif
else
abort();
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_or_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicOr32Barrier(i, p);
|
| ︙ | | | ︙ | |
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392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
|
static OF_INLINE unsigned int
of_atomic_and_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_THREADS)
return (*p &= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %2, %%eax\n\t"
"andl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax"
);
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_and_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicAnd32Barrier(i, p);
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|
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467
468
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470
471
472
473
474
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476
477
478
479
480
481
482
483
484
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486
487
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490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
|
static OF_INLINE unsigned int
of_atomic_and_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_THREADS)
return (*p &= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
if (sizeof(int) == 4)
__asm__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %2, %%eax\n\t"
"andl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax"
);
# ifdef OF_AMD64_ASM
if (sizeof(int) == 8)
__asm__ (
"0:\n\t"
"movq %2, %0\n\t"
"movq %2, %%rax\n\t"
"andq %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "rax"
);
# endif
else
abort();
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_and_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicAnd32Barrier(i, p);
|
| ︙ | | | ︙ | |
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
|
static OF_INLINE unsigned int
of_atomic_xor_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_THREADS)
return (*p ^= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
__asm__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %2, %%eax\n\t"
"xorl %1, %0\n\t"
"lock\n\t"
"cmpxchgl %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax"
);
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_xor_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicXor32Barrier(i, p);
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>
>
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|
545
546
547
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549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
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573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
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static OF_INLINE unsigned int
of_atomic_xor_int(volatile unsigned int *p, unsigned int i)
{
#if !defined(OF_THREADS)
return (*p ^= i);
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
if (sizeof(int) == 4)
__asm__ (
"0:\n\t"
"movl %2, %0\n\t"
"movl %2, %%eax\n\t"
"xorl %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "eax"
);
# ifdef OF_AMD64_ASM
if (sizeof(int) == 8)
__asm__ (
"0:\n\t"
"movq %2, %0\n\t"
"movq %2, %%rax\n\t"
"xorq %1, %0\n\t"
"lock\n\t"
"cmpxchg %0, %2\n\t"
"jne 0\n\t"
: "=&r"(i)
: "r"(i), "m"(*p)
: "rax"
);
# endif
else
abort();
return i;
#elif defined(OF_HAVE_GCC_ATOMIC_OPS)
return __sync_xor_and_fetch(p, i);
#elif defined(OF_HAVE_OSATOMIC)
if (sizeof(int) == 4)
return OSAtomicXor32Barrier(i, p);
|
| ︙ | | | ︙ | |
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
|
if (*p == o) {
*p = n;
return YES;
}
return NO;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
int r;
__asm__ (
"xorl %0, %0\n\t"
"lock\n\t"
"cmpxchg %2, %3\n\t"
"jne 0\n\t"
"incl %0\n"
|
|
|
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
|
if (*p == o) {
*p = n;
return YES;
}
return NO;
#elif defined(OF_X86_ASM) || defined(OF_AMD64_ASM)
int32_t r;
__asm__ (
"xorl %0, %0\n\t"
"lock\n\t"
"cmpxchg %2, %3\n\t"
"jne 0\n\t"
"incl %0\n"
|
| ︙ | | | ︙ | |